The present invention relates to a semiconductor storage element and a method of manufacturing it.
In order to reduce the power consumption and the size of electronic equipments, there is a demand for a nonvolatile semiconductor storage element which consumes a small electric power and provides a high integration density. To achieve such a semiconductor storage element, the semiconductor storage element is required to be able to be constituted of a reduced number of components and in a small area. A known semiconductor storage device having a highest degree of integration is a DRAM (Dynamic Random Access Memory) whose memory cells each consist of one transistor and one capacitor. However, the efforts to further increase the degree of integration of the DRAM by simply reducing the size of the memory cells almost reach the limit. One reason for that is that it has become technically difficult to further pursue the fineness or smallness. Even if it is technically possible to do so, use of high techniques is required, so that the cost for manufacturing the DRAM becomes considerably high. Another reason is as follows. In the DRAM, information is stored by accumulating a charge in the capacitor. In order to reliably read a charge amount accumulated in the capacitor, it is necessary for the capacitor to have a certain capacity (several tens of fF/cell). Therefore, it is difficult to form the capacitor in a smaller area.
To overcome the problem, there are proposed the following semiconductor storage elements (1) and (2) each constituted of a small number of components and having an information storage function in a small area (Japanese Laid-Open Patent Publication No. 7-111295).
(1) A semiconductor storage element having a source region and a drain region, wherein the source region is connected with the drain region through a channel region; the channel region is connected with a gate electrode through a gate insulation film; a level for capturing at least one carrier is formed proximately to a current path of the channel region positioned between the source region and the drain region; and an effective capacity Cgc between the gate electrode and the channel region satisfies the following inequality: EQU 1/Cgc&gt;kT/q.sup.2 equation (1)
where k: Boltzmann's constant, T: operation temperature, and q: charge amount of electron
(2) A semiconductor storage element having a source region and a drain region, wherein the source region is connected with the drain region through a channel region; the channel region is connected with a gate electrode through a gate insulation film; at least one carrier trap region is formed proximately to a current path of the channel region positioned between the source region and the drain region; a potential barrier is provided between the channel region and the carrier trap region; a capacity C between the channel region and the carrier trap region is set to be greater than a capacity Cgt between the gate electrode and the carrier trap region; and the whole capacity Ctt of the carrier trap region satisfies the following inequality: EQU q.sup.2 /(2Ctt)&gt;kT equation (2)
where k: Boltzmann's constant, T: operation temperature, and q: charge amount of electron
FIG. 4 is a graph showing the dependence of a drain current on the voltage between the gate and the source in each of the semiconductor storage elements (1) and (2). As shown in FIG. 4, when a gate voltage Vgs is vertically swept between Vg0 and Vg1, the conductance between the source and the drain exhibits a hysteresis at the room temperature. That is, whether a carrier has been captured can be detected in terms of the magnitude of electric current. This indicates that a semiconductor storage device can be realized by controlling the semiconductor storage element (1) or (2) with a data line and a word line.
In the Japanese Laid-Open Patent Publication No. 7-111295, there are disclosed concrete examples of the semiconductor storage elements (1) and (2) which are shown in FIGS. 5A, 5B, 5C, and 5D and FIGS. 6A and 6B, respectively.